1. Field of the Invention
The invention relates to an electronic memory and, more particularly, to a biasing circuit designed to bias the memory cells in groups.
2. Description of the Related Art
Memories are known electronic circuits that are in increasing use. A memory circuit comprises a plurality of storage cells organized in rows and columns. Each storage cell stores one data bit, that is to say a bit of information that can take the value “0” or “1”. Address lines connect all the cells of the same row together in order to allow the selection of a row from amongst the plurality of rows forming the memory. Bit lines connect the cells of the same column together in order to allow the reading and writing of a bit in a memory cell belonging to a bit line and whose address line is selected.
The storage cells can be of various types depending on the type of memory used. Among the various types of storage cells, those having at least one transistor linking the element storing the data bit to the bit line are of more particular interest. By way of example, memories of the static RAM type generally have one or two link transistors for connecting the contents of the cell to one or two bit lines depending on whether the read operation is carried out directly on a single bit line, or differentially between two complementary bit lines. Also, some memories of the ROM type have a link transistor for connecting the contents of the storage cell to the bit line.
Memory circuits are continually increasing in size. Thus, a bit line for a large-sized memory may be connected to several hundred, or even several thousand, link transistors. In order to read a storage cell, an address line selects a storage cell whereas all the other address lines do not select any storage cells in the same column. The storage cell being read has its link transistor turned on and a large conduction current appears for charging or discharging the bit line in order to transmit the logic level stored by the cell to a read circuit.
One problem arises when there is a very large number of link transistors connected to a bit line, since the link transistors, even when turned off, exhibit a leakage current that becomes non-negligible when this leakage current is multiplied by a large number of link transistors. The problem is even more acute when it is desired to read a cell in a particular state, for example a “1” state corresponding to a high voltage, while all the other cells not selected are in the other state, for example the “0” state corresponding to a low voltage. Indeed, the sum of the leakage currents over the whole of the transistors may greatly reduce the read current delivered by the selected cell, thus greatly increasing the time required for reading a memory cell. But in the case of static RAM memories, if the leakage current is too large, this can make the state of the selected storage cell, and hence the stored value, change.
Currently, one solution to the aforementioned problem consists in using main bit lines and secondary bit lines. The secondary bit lines are parallel to the main bit lines and are connected to a reduced number of cells, for example 32 cells. A transfer gate links each secondary bit line to the main bit line. Thus, when a storage cell is selected, only the leakage currents of the group of cells connected to the same secondary bit line can influence the read time and the possible loss of data from the cell. However, in terms of read time, the propagation time through the link transistor and through the transfer gate is relatively long. Also, in terms of size, the bit lines are lines of metallization which must be disposed where no cell is situated and, therefore, doubling the number of bit lines by means of main and secondary lines is detrimental to the capacity for integration of a memory.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.